Learn › Topic 12

Timing diagrams, glitches and static hazards

8 min read · bitGateLab Team

On paper a gate responds instantly; in reality every gate takes a few nanoseconds. That difference almost never matters in the truth table, but it does in the timing diagram: two paths with different delays can produce false pulses, called glitches, that advance a counter or trigger a latch when they should not. Here you will learn to read a timing diagram, compute delays, and detect and remove static hazards with the Karnaugh map.

How to read a timing diagram

A timing diagram draws each signal as a line that goes up (1) or down (0) over a shared horizontal time axis. An imaginary vertical line at any instant gives you the value of every signal. The input edges are the causes; the distance between an input edge and the change it causes at the output is the delay. In clocked circuits, read the values just before each active edge, which is when the flip-flops sample.

Propagation delay and critical path

The propagation delay is the time between a change at the input and the resulting change at the output, measured between the 50% points of each transition. Two values are distinguished:

t_PLH: the delay when the output goes from low to high.
t_PHL: the delay when the output goes from high to low.

In the 74HC family powered at 5 V, the delays of a simple gate are on the order of 10 ns, and they grow with the capacitive load and as the supply voltage is lowered.

The delay of a circuit is that of the slowest path between any input and the output, the critical path. It is computed by adding up the gate delays along each path and keeping the largest total.

Example: F = A·B + A·C with t_NOT = 5 ns, t_AND = 10 ns and t_OR = 10 ns.

Path from B or from C: AND + OR = 20 ns.
Path from A through the upper AND: AND + OR = 20 ns.
Path from A through the inverter: NOT + AND + OR = 25 ns.

The critical path is the one from A through the inverter, at 25 ns. No input change takes longer than that to leave F stable.

Glitches and static hazards

A static-1 hazard exists when the output should stay at 1 during an input change, but may briefly drop to 0. A static-0 hazard is the opposite: the output should stay at 0 and produces a brief spike to 1. Both appear when a variable and its complement reach the output through paths with different delays.

Take the circuit from the previous example with B = C = 1. Logically, F = A + A = 1 always. But when A falls from 1 to 0, the term A·B turns off before A·C turns on, because A has to go through the inverter first.

With B = C = 1, A falls at t = 0. Between 10 and 15 ns both inputs of the OR are 0, and F drops from 20 to 25 ns: a 5 ns glitch.

Timeline of the glitch (B = C = 1, A falls at t = 0):

t = 5 ns: the inverter raises A.
t = 10 ns: the AND for A·B lowers its output (it responded to the change of A at t = 0).
t = 15 ns: the AND for A·C raises its output (it responded to the change of A at t = 5).
Between 10 and 15 ns both inputs of the OR are 0. The OR responds 10 ns later: F is 0 from t = 20 to t = 25 ns.

The width of the glitch is the difference in delay between the two paths: 5 ns, the inverter's delay. If A rises, A·B turns on at t = 10 and A·C turns off at t = 15; both are 1 during that interval and there is no glitch.

There are also dynamic hazards: the output should change only once and it changes three or more times (for example 1 → 0 → 1 → 0). They appear in multi-level logic with three or more paths of different delay for the same variable.

Detecting and removing hazards with Karnaugh maps

On the Karnaugh map of a sum of products, a static-1 hazard appears when two cells holding a 1 are adjacent but are covered by different groups, and no group covers both. Moving from one cell to the other means changing a single variable, and during that change the circuit "jumps" from one term to another.

The solution is to add the consensus term: an extra group that covers both cells. It is redundant from a logical point of view (it does not change the truth table), but it keeps the output at 1 during the transition.

Example: F = A·B + A·C.

A·B covers the cells ABC = 110 and 111. A·C covers 001 and 011.
Cells 011 and 111 are adjacent (only A changes) and belong to different groups: that is the hazard we saw, with B = C = 1.
The group that covers both is B·C, the consensus of A·B and A·C: drop the variable that appears true in one term and complemented in the other, and multiply what is left.
Hazard-free circuit: F = A·B + A·C + B·C. With B = C = 1, the term B·C is 1 the whole time and the OR can no longer drop.

For a product of sums the reasoning is the dual: look for adjacent zeros in different groups and add the consensus sum to remove the static-0 hazard. For example, F = (A + B)·(A + C) has a hazard when B = C = 0, and it is fixed by adding the factor (B + C).

Adding consensus terms removes static hazards caused by a single variable change. In synchronous design the other defense is not to look at the combinational logic while it settles: flip-flops sample only at the clock edge, when the glitches are already over. Glitches are dangerous, however, on clocks, asynchronous resets and latch enables.

Common mistakes

Thinking that a circuit with the correct truth table cannot fail: the table says nothing about the behavior during transitions.
Removing the consensus term "because it is redundant" when simplifying, in a circuit that drives a clock or a reset.
Adding up the delays of every gate in the circuit instead of only those along the slowest path.
Believing that the consensus term removes glitches when two inputs change at the same time: it only covers changes of one variable.

Try it in the simulator

In the timing diagram you can see the spike and how it disappears when the consensus term is added.

Place an inverter, two AND gates and an OR, and build F = A·B + A·C.
Set B = 1 and C = 1, and connect A to an input you can toggle or to a slow clock signal.
Open the timing diagram and change A from 1 to 0 several times; watch F at the moment of the transition and see whether a brief pulse or a glitch notice appears.
Add a third AND with B·C and feed it into the OR.
Repeat the change of A and observe that F stays at 1.

Exercises

Find the static hazard of F = A·C + B·C and write the hazard-free version.
Answer
A·C covers 100 and 110; B·C covers 011 and 111. Cells 110 and 111 are adjacent (C changes) and in different groups, with A = B = 1. Consensus: A·B. F = A·C + B·C + A·B.
In the circuit of exercise 1, with t_NOT = 4 ns, t_AND = 8 ns and t_OR = 8 ns, A = B = 1, on which transition of C does the glitch appear, when, and how long does it last?
Answer
When C falls at t = 0: B·C falls at t = 8, C rises at t = 4 and A·C rises at t = 12. Between 8 and 12 ns the OR sees two zeros, so F is 0 from t = 16 to t = 20 ns: 4 ns. When C rises there is no glitch.
What is the critical path of F = A·C + B·C with the delays from exercise 2?
Answer
From C through the inverter: 4 + 8 + 8 = 20 ns.
For F = (A + B)·(A + C), what value should the output have when B = C = 0, and what glitch can appear?
Answer
With B = C = 0, F = A·A = 0. When A changes, a brief spike to 1 can appear (static-0 hazard). It is removed by adding the factor (B + C).