Learn › Topic 9

Latches and flip-flops: SR, D, JK and T step by step

7 min read · bitGateLab Team

Until now the outputs of your circuits depended only on the inputs at that moment. To count, store a value or remember which step a process is in, you need memory, and the smallest memory cell is the latch. Here you will build a latch from two gates, turn it into an edge-triggered flip-flop and use the tables you will need to design counters and state machines.

The SR latch

Two NOR gates with their outputs crossed back to each other's inputs form an SR latch. The feedback is what creates the memory: once the output takes a value, it holds itself there.

With S = R = 1 both NOR gates output 0, so Q and Q are no longer complementary. Worse still: if both inputs then drop to 0 at the same time, the final state depends on which gate is faster. That is why this combination is forbidden. Its characteristic equation, valid under the condition S·R = 0, is Q+ = S + R·Q.

With NAND gates you get the SR latch, which has active-low inputs: 11 holds, 01 sets Q = 1, 10 sets Q = 0 and 00 is the forbidden combination (both outputs at 1).

The D latch: transparent while enabled

To eliminate the forbidden combination, an enable input EN is added and the signals S = D·EN and R = D·EN are generated. Since S and R are never 1 at the same time, the problem goes away. The behavior is simple:

• EN = 1: the latch is transparent, Q follows D at all times.
• EN = 0: Q freezes at the last value D had.

Transparency is the latch's weakness. If you connect the output of a latch, through logic, back to its own input, then while EN = 1 the signal can go around the loop several times and the result is unpredictable. Synchronous sequential circuits need something that captures the data at a single instant.

Edge-triggered flip-flops

A rising-edge-triggered D flip-flop copies D to Q only at the instant the clock goes from 0 to 1. The rest of the time it ignores D. It is built from two D latches in cascade (master and slave) with opposite enables: while the clock is at 0 the master follows D and the slave is closed; when the clock rises the master closes and the slave passes the captured value to the output. Its equation is the simplest of all: Q+ = D.

Starting from the basic flip-flop, two other types widely used in design are defined:

• JK: like the SR but with no forbidden combination. J = K = 1 makes Q change (toggle) on every edge. Equation: Q+ = J·Q + K·Q.
• T (toggle): with T = 0 it holds, with T = 1 it toggles. Equation: Q+ = T ⊕ Q. It is obtained from a JK with J = K = T or from a D with D = T ⊕ Q.

Excitation tables

The characteristic table answers "given the inputs, where does Q go?". Design needs the reverse question: "I want Q to go from this value to that one; which inputs do I apply?". That is the excitation table, and you will use it in every counter and state machine.

The X's of the JK are the reason this flip-flop usually gives shorter equations: to go from 0 to 1 it makes no difference whether K is 0 (set) or 1 (toggle), and that freedom is exploited on the Karnaugh map.

Setup time, hold time and maximum frequency

A real flip-flop needs D to be stable for some time before the edge, the setup time (t_su), and to remain stable for some time after it, the hold time (t_h). If D changes inside that window, the output may sit at an intermediate level for a while before making up its mind: this is metastability. In addition, the output takes a delay t_CQ to change after the edge.

In a synchronous circuit the signal leaves one flip-flop, crosses combinational logic and arrives at the next. The minimum clock period is:

Tmin = tCQ + tlogic + tsu

Common mistakes

• Calling a latch a flip-flop: the latch responds to the level of the enable, the flip-flop to the clock edge.
• Using the characteristic table when the design calls for the excitation table.
• Forgetting that in the NAND latch the inputs are active-low and that the forbidden combination is 00, not 11.
• Changing D right at the clock edge and expecting a defined result.
• Leaving the asynchronous preset and clear inputs of a real flip-flop unconnected: they must be tied to their inactive level.

Try it in the simulator

The difference between a latch and a flip-flop shows up immediately in a timing diagram. Build both and feed them the same signal.

1. Place two NOR gates and connect the output of each one to an input of the other; add inputs S and R and two indicators.
2. Change S and R to check the four rows of the table, including the forbidden one, and observe that Q and Q are both 0 at the same time.
3. Place a D latch and a D flip-flop, and connect the same data input and the same clock or enable signal to both.
4. Open the timing diagram and change D several times while the clock is at 1: the latch follows the changes and the flip-flop only takes the value at the rising edge.
5. Repeat with a JK flip-flop with J = K = 1 and observe that its output has half the clock frequency.

Exercises

1. A T flip-flop starts at Q = 1 and receives T = 1, 1, 0, 1 on four edges. What values does Q take?
   Answer

   Q⁺ = T ⊕ Q: 1⊕1 = 0, 1⊕0 = 1, 0⊕1 = 1, 1⊕1 = 0. Sequence: 0, 1, 1, 0.

2. What values of J and K do you need for a flip-flop to go from Q = 1 to Q = 0?
   Answer

   J = X, K = 1. With K = 1 and J = 0 it resets; with J = K = 1 it toggles. Both options take Q to 0.

3. With t_CQ = 12 ns, t_su = 4 ns and a target frequency of 40 MHz, how long can the logic between flip-flops take at most?
   Answer

   T = 1 / 40 MHz = 25 ns. t_logic ≤ 25 − 12 − 4 = 9 ns.

4. Write the equation for D that makes a D flip-flop behave like a JK.
   Answer

   D = J·Q + K·Q, which is the characteristic equation of the JK.

With these building blocks you can now move on to counters and registers and then to state machines.