Learn › Topic 10

Counters and shift registers: step-by-step design

7 min read · bitGateLab Team

A counter is a group of flip-flops that steps through a fixed sequence of states with each clock pulse; a register is a group of flip-flops that stores or shifts a binary word. They are used to measure time, divide frequencies, convert data from serial to parallel and generate control sequences. You need to be comfortable with D, JK and T flip-flops and their excitation tables, which are explained in latches and flip-flops.

Asynchronous (ripple) counter

The simplest way to count is to chain T flip-flops with T = 1, so that each one toggles and divides the frequency by 2. Only the first one receives the system clock; each of the following ones takes the output of the previous one as its clock. With falling-edge-triggered flip-flops, Q of one stage is connected to the clock of the next and the counter counts up; with rising-edge ones you have to use Q to count up (with Q it would count down).

Its drawback is the accumulated delay: stage n does not change until all the previous ones have changed, like a wave travelling down the chain. During that time the output passes through false values.

Example: a 4-bit asynchronous counter with t_CQ = 12 ns per flip-flop. It goes from 0111 to 1000.

Q0 changes from 1 to 0 at 12 ns: the output reads 0110.
Q1 changes at 24 ns: 0100.
Q2 changes at 36 ns: 0000.
Q3 changes at 48 ns: 1000, the correct value.

For 48 ns the output showed 0110, 0100 and 0000. If a circuit decodes those values, it will see false pulses. To always read a stable value the clock period must exceed 48 ns, that is, f < 20.8 MHz.

Synchronous counter

In a synchronous counter all the flip-flops receive the same clock, and logic decides which ones toggle. In a binary up counter, a bit toggles when all the less significant bits are 1:

T0 = 1, T1 = Q0, T2 = Q0·Q1, T3 = Q0·Q1·Q2

All the outputs change together, t_CQ after the edge. The minimum period no longer grows with the number of bits because of the flip-flop chain; it depends on t_CQ + the AND delay + t_su.

Modulo-N counter

A modulo-N counter steps through N states and starts over. It needs at least ⌈log₂ N⌉ flip-flops. There are two ways to build one.

With asynchronous reset: take a binary counter and detect the first state that must not appear. For modulo 10 that state is 1010; a NAND of Q3 and Q1 connected to the active-low clear is enough, because it is the first time Q3 and Q1 are both 1. It works, but the state 1010 appears for a few nanoseconds and produces a short pulse on the outputs.

Synchronous design: write the state table and compute the inputs with the excitation table. There are no transient states.

Example: a synchronous modulo-6 counter (0 to 5) with T flip-flops. States Q2 Q1 Q0; the states 110 and 111 are unused and count as X.

Q2 Q1 Q0	Next	T2	T1	T0
000	001	0	0	1
001	010	0	1	1
010	011	0	0	1
011	100	1	1	1
100	101	0	0	1
101	000	1	0	1

Each T is 1 when its bit changes. Simplifying with the X's:

T0 = 1.
T1 = Q2·Q0 (covers 001 and 011; in 101 it is 0 because Q2 = 1).
T2 = Q1·Q0 + Q2·Q0 = Q0·(Q1 + Q2).

Check the unused states: from 110, T2 = 0, T1 = 0, T0 = 1, the counter goes to 111; from 111, T2 = 1, T1 = 0, T0 = 1, it goes to 010. Both return to the sequence: the counter is self-starting even if it powers up in an invalid state.

Shift registers

A shift register is a chain of D flip-flops: the output of each one feeds the input of the next and, on every edge, all the bits move one position. They are classified by how the data goes in and comes out:

SISO (serial in, serial out): delays a signal by n clock cycles.
SIPO (serial in, parallel out): receives bits one at a time and delivers them together. It converts serial to parallel.
PISO (parallel in, serial out): loads a whole word and shifts it out bit by bit. Each flip-flop has a 2-to-1 MUX on its input: D_i = LOAD·P_i + LOAD·Q_i−1.
PIPO (parallel in, parallel out): a plain storage register.

Example: a 4-bit SIPO register, initially at 0000, with Q0 ← input, Q1 ← Q0, Q2 ← Q1, Q3 ← Q2. The bits 1, 0, 1, 1 are sent in that order.

Edge	Input bit	Q0 Q1 Q2 Q3
1	1	1 0 0 0
2	0	0 1 0 0
3	1	1 0 1 0
4	1	1 1 0 1

After 4 edges, read as Q3 Q2 Q1 Q0, the register holds 1011: the first bit sent ended up in Q3.

Ring counter and Johnson counter

If the output of the last flip-flop of a shift register is connected to the input of the first, you get a ring counter. It is initialized with a single 1 (for example 1000) and that 1 circulates: 1000, 0100, 0010, 0001, 1000. With n flip-flops it has n states and every state comes already decoded, because only one output is at 1. The initial load must be guaranteed; if it starts at 0000 it stays there forever.

If Q of the last flip-flop is fed back instead of Q, you get the Johnson counter (or twisted-ring counter), with 2n states. For 4 bits (Q0 Q1 Q2 Q3, with Q0 ← Q3):

0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000

Each state can be told apart with an AND of just two inputs, by looking at where the boundary between ones and zeros lies: for example, 1100 is the only one with Q1 = 1 and Q2 = 0, and 0000 is the only one with Q0 = 0 and Q3 = 0.

For 4 flip-flops: a binary counter uses all 16 states, a Johnson counter uses 8 and a ring counter uses 4. The leftover states of the Johnson counter (8) and of the ring counter (12) must be corrected with extra logic if the circuit can start up in one of them.

Common mistakes

Decoding the outputs of an asynchronous counter with combinational logic without taking the transient states into account.
Connecting Q instead of Q between the stages of a rising-edge asynchronous counter and getting a down counter.
Forgetting to check where the unused states of a modulo-N counter go.
Starting a ring counter without loading the initial 1.
Mixing up the bit order when reading a SIPO register: the first bit in ends up at the far end.

Try it in the simulator

Comparing an asynchronous counter with a synchronous one in the timing diagram is the best way to see the ripple effect.

Place four T flip-flops with T = 1, connect the clock to the first one and chain the rest as an asynchronous counter.
Connect the four outputs to indicators and to a display or an LED bar graph.
Next to it, build the synchronous counter with T1 = Q0, T2 = Q0·Q1 and T3 = Q0·Q1·Q2, all with the same clock.
Open the timing diagram, let the clock run and watch the transition from 0111 to 1000 in both.
Build a register of four D flip-flops in a chain, change the serial input before each edge and watch the bits move along; then feed Q of the last stage back to the first and verify the 8 states of the Johnson counter.

Exercises

How many flip-flops do you need for a modulo-12 counter built as a binary, a ring and a Johnson counter?
Answer
Binary: 4 (2⁴ = 16 ≥ 12). Ring: 12. Johnson: 6 (2 × 6 = 12).
Which gate and which outputs would you use to build a modulo-12 counter with an active-low asynchronous reset starting from a 4-bit binary counter?
Answer
12 = 1100. A NAND of Q3 and Q2 connected to the clear, because it is the first time both are 1.
An 8-bit asynchronous counter uses flip-flops with t_CQ = 10 ns. What is the worst-case settling time?
Answer
8 × 10 = 80 ns, for example when going from 01111111 to 10000000.
Which two-input AND decodes the state 0111 of the 4-bit Johnson counter?
Answer
Q0·Q1: it is the only state with Q0 = 0 and Q1 = 1.